1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an improved semiconductor memory device capable of restraining noise generation when a cell data signal is applied to an output buffer.
2. Description of the Prior Art
As disclosed in U.S. Pat. No. 5,043,944, a conventional semiconductor memory device for improving an output characteristic as shown in FIG. 1 includes: an X decoder 10 for decoding a row address signal outputted from an X address buffer (not shown); a Y decoder 11 for decoding a column address signal outputted from a Y address buffer (not shown) in accordance with a Y address latch signal YLB; a memory cell array 12 for outputting a cell data set D,/D in accordance with respective address signals decoded in the X decoder 10 and the Y decoder 11; and an output buffer 13 for buffering the output data of the memory cell array 12 in accordance with a data output enable signal DOE and applying the buffered output data to an input/output pin 14.
The operation of the thusly constituted conventional semiconductor memory device will now be described.
As shown in FIGS. 2A and 2B, when an output enable signal is externally enabled, a DRAM controller circuit (not shown) generates a data output enable signal DOE for controlling output buffer 13, and a Y address latch signal YLB for controlling an output of memory cell array 12.
The X decoder 10 decodes a row address signal outputted from an X address buffer (not shown) and outputs the decoded signal to a row decoder (not shown), which decodes an input signal and designates a row address in the memory cell array 12.
The Y decoder 11 decodes a column address signal outputted from a Y address buffer (not shown) and outputs the decoded signal to a column decoder (not shown) in accordance with Y address latch signal YLB. The column decoder decodes an input signal and designates a column address in the memory cell array 12.
The memory cell array 12 records data in memory cells designated by an address signal or reads data stored in the memory cells in accordance with the row address signal and the column address signal, respectively. In accordance with data output enable signal DOE, the output buffer 13 buffers and applies to the input/output pin 14 a cell data set D,/D outputted from the memory cell array 12.
Here, Y address latch signal YLB is enabled after data output enable signal DOE is enabled, so that as shown in FIG. 2A, the turning of Y address latch signal YLB to a low level denotes that the cell data set D,/D outputted from the memory cell array 12 are applied to an input terminal of the output buffer 13.
However, because the cell data set D,/D are instantly applied to the output buffer 13 at a time t when the Y address latch signal YLB is turned to a low level, as shown in FIG. 2C there occurs a ground noise.